Synchronizing circuit for generating a signal synchronizing with a clock signal

ABSTRACT

A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of U.S. patent application Ser.No. 09/505,204, filed Feb. 16, 2000, which is based upon and claims thebenefit of priority from the prior Japanese Patent Application No.11-038574, filed Feb. 17, 1999, the entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] This invention relates to a synchronizing circuit which generatesa signal synchronizing with an external clock signal and is applied to,for example, a synchronous DRAM.

[0003] One known circuit for generating an internal clock signalsynchronizing with an external clock signal is a SAD (SynchronousAdjustable Delay) synchronizing circuit. This type of synchronizingcircuit supplies an external clock signal to a first delay line composedof unit delay elements without using a feedback loop. The period of theclock signal transferred to the first delay line is measured directly.Information on the measured period is stored in a state holding section.On the basis of the information stored in the state holding section, anew clock signal is supplied to a second delay line composed of unitdelay elements. This produces a clock signal which synchronizes with theexternal clock and lags behind by an integral multiple of the periodfrom the external clock signal.

[0004] In this type of synchronizing circuit, the accuracy with whichthe internal clock signal synchronizes with the external clock signaldepends on the amount of delay in the unit delay elements. To transferdata at high speed, it is necessary to increase the frequency of theclock signal. When the frequency of the clock signal has increased tosuch an extent that it cannot be ignored as compared with the amount ofdelay in the unit delay elements, the accuracy of synchronization candecrease.

BRIEF SUMMARY OF THE INVENTION

[0005] It is, accordingly, an object of the present invention toovercome the above problem by providing a synchronizing circuit capableof improving the accuracy of synchronization even when the frequency ofthe clock has increased.

[0006] The foregoing object is accomplished by providing a synchronizingcircuit comprising: a first delay line which includes unit delayelements and transfers a forward pulse signal; a second delay line whichincludes unit delay elements and transfers a backward pulse signal; anda state holding section which senses the transfer position of theforward pulse signal transferred along the first delay line and controlsthe backward pulse signal transferred along the second delay line,wherein each of the unit delay elements constituting the first andsecond delay lines has transistors including first and secondtransistors, the current driving capability of the first transistorsbeing set higher than that of the second transistors, the firsttransistors making a response when the signal inputted to the unit delayelements changes from a first level to a second level higher than thefirst level, and the second transistors making a response when thesignal inputted to the unit delay elements changes from the second levelto the first level.

[0007] With the present invention, the current driving capability of thetransistors related to the rising of the pulse signal in the unit delayelements is increased. As a result, the rise time of the pulse signal ismade shorter, which improves the accuracy of synchronization, even whenthe frequency of the clock signal gets higher. In addition, the pulsewidth of the signal passed through the unit delay elements can be keptconstant.

[0008] The foregoing object is also accomplished by providing asynchronizing circuit comprising: a first delay line which includes unitdelay elements and transfers a forward pulse signal; a second delay linewhich includes as many unit delay elements as equals half the number ofthe unit delay elements the first delay line has and which transfers abackward pulse signal; and a state holding section including stateholding circuits arranged so as to correspond to the unit delay elementsconstituting the first and second delay lines, the state holdingcircuits being set by the forward pulse signal transferred along thefirst delay line and reset by the backward pulse signal transferredalong the second delay line and having a set state in which a pair ofadjacent ones of the state holding circuits have been set, a reset statein which a pair of adjacent ones of the state holding circuits have beenreset, and an intermediate state in which one of a pair of adjacent onesof the state holding circuits is set and the other of the pair is reset.

[0009] With the present invention, the accuracy of synchronization canbe improved to half the amount of delay in a unit delay element and aclock signal delayed for half the period can be generated from theinputted clock signal.

[0010] Furthermore, the foregoing object is accomplished by providing asynchronizing circuit comprising: a first delay line which includes unitdelay elements and transfers a forward pulse signal; a second delay linewhich includes unit delay elements and transfers a backward pulsesignal; and a state holding section including state holding circuitsarranged so as to correspond to the unit delay elements constituting thefirst delay line, the state holding circuits being set according to theforward pulse signal transferred along the first delay line and resetaccording to the backward pulse signal transferred along the seconddelay line and having a set state in which n adjacent ones (n is aninteger equal to or larger than 2) of the state holding circuits haveall been set, a reset state in which all of the n adjacent state holdingcircuits have been reset, and (n−1) intermediate states in which the nadjacent state holding circuits are either set or reset.

[0011] With the present invention, the second clock signal issynchronized with the first clock signal with the accuracy ofsynchronization of {fraction (1/n)} the amount of delay in a unit delayelement, which improves the accuracy of synchronization.

[0012] Still furthermore, the foregoing object is accomplished byproviding a synchronizing circuit comprising: n division circuits fordividing a first clock signal into n signals with an n-fold period (n isan integer equal to or larger than 2); n synchronizing circuits to whichthe signals divided by the n division circuits are suppliedrespectively; and a generator circuit for combining the output signalsof the n synchronizing circuits and producing a second clock signal withthe same period as that of the first clock signal.

[0013] With the present invention, the second clock signal issynchronized with the first clock signal with the accuracy ofsynchronization of {fraction (1/n)} the amount of delay in a unit delayelement. This makes it possible to improve the accuracy ofsynchronization more, even when the frequency of the clock signal getshigher.

[0014] Moreover, the foregoing object is accomplished by providing adelay circuit comprising: a clocked inverter circuit to which an inputpulse signal is supplied; and a logic circuit to which a pulse signaloutputted from the clocked inverter circuit and the inverted signal ofthe input pulse signal are supplied, wherein the clocked invertercircuit changes the pulse width of the input pulse signal in thedirection opposite to the direction in which the pulse width of thepulse signal outputted from the logic circuit changes.

[0015] In the present invention, the delay circuit is composed of acircuit for widening the pulse width and a circuit for narrowing thepulse width, which prevents the pulse width from getting narrower.

[0016] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0017] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0018]FIG. 1 shows the configuration of a SAD synchronizing circuitapplied to a first embodiment of the present invention;

[0019]FIGS. 2A, 2B, and 2C are circuit diagrams of part of a first and asecond delay line and a state holding section shown in FIG. 1;

[0020]FIG. 3 is a circuit diagram showing a unit delay element of FIG.2A;

[0021]FIG. 4A is a circuit diagram showing a unit delay element of FIG.2C, and

[0022]FIGS. 4B, 4C, and 4D are plan views to explain a method of settingthe current driving capability of each transistor;

[0023]FIG. 5 is a waveform diagram showing the signals at varioussections in FIGS. 1 to 4;

[0024]FIG. 6 shows the configuration of a synchronizing circuitaccording to a second embodiment of the present invention;

[0025]FIGS. 7A and 7B schematically show the operation of the stateholding section of FIG. 6;

[0026]FIGS. 8A, 8B, and 8C schematically show the operation of the stateholding section of FIG. 6;

[0027]FIG. 9 shows the configuration of FIG. 6;

[0028]FIG. 10 is a circuit diagram of part of FIG. 9;

[0029]FIG. 11 is a circuit diagram showing a unit delay element in FIG.10;

[0030]FIG. 12 is a circuit diagram showing a unit delay element in FIG.10;

[0031]FIG. 13 is a waveform diagram showing the operations of FIGS. 9 to12;

[0032]FIGS. 14A and 14B are diagrams to help explain intermediate state“M”;

[0033]FIG. 15 shows the configuration of the synchronizing circuit toexplain a modification of the second embodiment;

[0034]FIG. 16 is a circuit diagram of part of FIG. 15;

[0035]FIG. 17 is a circuit diagram of part of FIG. 16;

[0036]FIG. 18 shows the configuration of a third embodiment of thepresent invention;

[0037]FIG. 19 is a waveform diagram to explain the operation of FIG. 18;

[0038]FIGS. 20A to 20E show structures to explain a state holdingsection according to a fourth embodiment of the present invention;

[0039]FIG. 21 shows the configuration of part of the synchronizingcircuit according to the fourth embodiment;

[0040]FIG. 22 is a circuit diagram of part of FIG. 21;

[0041]FIG. 23 is a circuit diagram of part of FIG. 21;

[0042]FIG. 24 is a circuit diagram of part of FIG. 21;

[0043]FIG. 25 is a circuit diagram of part of FIG. 21;

[0044]FIG. 26 shows the configuration of a synchronizing circuitaccording to a fifth embodiment of the present invention;

[0045]FIG. 27 is a waveform diagram to explain the operation of FIG. 26;

[0046]FIG. 28 is a circuit diagram of a unit delay element including aclocked inverter circuit and a logic circuit;

[0047]FIG. 29 is a waveform diagram to explain the operation of FIG. 28;

[0048]FIG. 30A is a circuit diagram of a unit delay element using a NORcircuit and

[0049]FIG. 30B is a circuit diagram of a state holding circuit;

[0050]FIG. 31 is a circuit diagram of a unit delay element using a NORcircuit;

[0051]FIG. 32 is a circuit diagram showing a sixth embodiment of thepresent invention;

[0052]FIG. 33 is a waveform diagram to explain the operation of FIG. 32;

[0053]FIG. 34A is a circuit diagram to explain the optimization of aunit delay element and

[0054]FIG. 34B is a waveform diagram to explain the operation of FIG.34A;

[0055]FIG. 35 shows the result of simulation for optimizing the unitdelay element shown in FIG. 34A;

[0056]FIG. 36 is a circuit diagram showing a seventh embodiment of thepresent invention; and

[0057]FIG. 37 is a waveform diagram to explain the operation of FIG. 36.

DETAILED DESCRIPTION OF THE INVENTION

[0058] Hereinafter, referring to the accompanying drawings, embodimentsof the present invention will be explained.

[0059] First Embodiment

[0060] In a first embodiment of the present invention, the amount ofdelay in a unit delay element directly related to the accuracy ofsynchronization is decreased to improve the accuracy of synchronizationof an internal clock signal synchronized with an external clock signal.

[0061]FIG. 1 shows a SAD synchronizing circuit 11 applied to the firstembodiment. An external clock signal ECK is supplied to a delay monitor13 via an input buffer circuit 12 with a delay time of D1. The delaymonitor 13 has a delay time of D1+D2, which is the sum of the delay timeD1 of the input buffer circuit 12 and the delay time D2 of an outputbuffer circuit explained later. The output signal Din of the delaymonitor 13 is supplied to a first delay line 14 acting as a forwardpulse delay line. The first delay line 14 is composed of unit delayelements (DL) 14 i−3, . . . , 14 i, . . . , 14 i+3 connected in series.

[0062] Near the first delay line 14, a second delay line 16 acting as abackward pulse delay line is provided. The second delay line 16 iscomposed of unit delay elements (DL) 16 i−3, . . . , 16 i, . . . , 16i+3 connected in series. A state holding section 15 is provided betweenthe first and second delay lines 14, 16. The state holding section 15 iscomposed of state holding circuits 15 i−3, . . . , 15 i, . . . , 15 i+3provided in such a manner that they correspond to the individual unitdelay elements constituting the first and second delay lines 14, 16. Thestate holding circuits 15 i−3, . . . , 15 i, . . . , 15 i+3 are set insequence according to the pulse signal transferred to the first delayline 14 and are reset in sequence according to the pulse signaltransferred to the second delay line 16. In the set state, the stateholding circuits connect the unit delay elements constituting the seconddelay line 16, whereas in the reset state, the state holding circuitsseparate the unit delay elements of the second delay line 16. A clocksignal CLK is supplied to each of the unit delay elements 16 i−3, . . ., 16 i, . . . , 16 i+3 constituting the second delay line 16. The outputbuffer circuit 17 is connected to the output terminal of the seconddelay line 16. The output buffer circuit 17 outputs an internal clocksignal ICK synchronizing with the external clock signal ECK at itsoutput terminal.

[0063] The external clock signal ECK is supplied to a first signalgenerator circuit 18. The first signal generator circuit 18 is composedof an inverter circuit 18 a, a delay circuit 18 b with a delay time ofd, a NOR circuit 18 c to which the output signals of the invertercircuit 18 a and delay circuit 18 b are supplied and which outputs asignal pa, and an inverter circuit 18 d to which the signal pa issupplied and which outputs an inverted signal bpa (hereinafter, “b” atthe head of a reference symbol means an inverted signal).

[0064] The clock signal CLK outputted from the input buffer 12 issupplied to a second generator circuit 19. The second signal generatorcircuit 19 is composed of an inverter circuit 19 a, a delay circuit 19 bwith a delay time of d, a NOR circuit 19 c to which the output signalsof the inverter circuit 19 a and delay circuit 19 b are supplied andwhich outputs a signal p, and an inverter circuit 19 d to which thesignal pa is supplied and which outputs an inverted signal bp.

[0065] The signal bp outputted from the second signal generator circuit19 and the output signal Dout of the second delay line 16 are suppliedto a third generator circuit 20. The third signal generator circuit 20is composed of a flip-flop circuit 20 a to which the signals bp and Doutare supplied, an inverter circuit 20 b to which the signal Dout issupplied, a NAND circuit 20 c to which the output signal of the invertercircuit 20 b and the output signal of the flip-flop circuit 20 a aresupplied, an inverter circuit 20 d to which the output signal of theflip-flop circuit 20 a is supplied, an inverter circuit 20 e to whichthe output signal of the inverter circuit 20 d is supplied, a delaycircuit 20 f with a delay time of d, a NAND circuit 20 g to which theoutput signal of the delay circuit 20 f and the output signal of theinverter circuit 20 d are supplied, a NAND circuit 20 h to which theoutput signals of the NAND circuit 20 g and NAND circuit 20 c aresupplied, and an inverter circuit 20 i to which the output signal of theNAND circuit 20 h is supplied and which outputs a signal bpm.

[0066] The signals pa and bpa outputted from the first signal generatorcircuit 18, the signals p and bp outputted from the second signalgenerator circuit 19, and the signal bpm outputted from the third signalgenerator circuit 20 are supplied to the first and second delay lines14, 16 and state holding section 15.

[0067]FIGS. 2A, 2B and 2C show the configuration of the unit delayelements 14 i and 16 i and state holding circuit 15 i at the i-th stagein the first and second delay lines 14, 16 and state holding section 15.The unit delay element 14 i is composed of clocked inverter circuits 14a, 14 b connected in series, inverter circuits 14 c, 14 d connected inseries with the output terminal of the clocked inverter circuit 14 b, ann-channel MOS transistor (hereinafter, referred to as an NMOStransistor) NM7 which is connected between the output terminal of theclocked inverter circuit 14 b and the ground and to whose gate a signalp is supplied, and a clocked inverter circuit 14 f whose input terminalis grounded and whose output terminal is connected to the input terminalof the clocked inverter circuit 14 b.

[0068] The clocked inverter circuits 14 a, 14 b, 14 f are controlled bythe signals p and bp. The signal Fi−1 outputted from the unit delayelement 14 i−1 at the (i−1)-th stage is supplied to the input terminalof the clocked inverter circuit 14 a. The clocked inverter circuit 14 boutputs a signal Fi at its output terminal. The inverter circuit 14 doutputs a signal FFi. The signals Fi and FFi are supplied to the unitdelay element 14 i+1 and state holding circuit 15 i+1, respectively.

[0069] The state holding circuit 15 i is composed of a clocked invertercircuit 15 a and inverter circuits 15 b, 15 c connected in series. Theclocked inverter 15 a is composed of p-channel MOS transistors(hereinafter, referred to as PMOS transistors) PM18 and PM17 and NMOStransistors NM18 and NM17 whose current paths are connected in seriesbetween a power supply Vcc and the ground.

[0070] The signal bRi−3 outputted from the unit delay element 16 i−3 atthe (i−3)-th stage constituting the second delay line 16 is supplied tothe gate of the PMOS transistor PM18. The signal bpm is supplied to thegates of the PMOS transistor PM17 and NMOS transistor NM18. The signalFFi−1 supplied from the unit delay element 14 i−1 at the (i−1)-th stageconstituting the first delay line 14 is supplied to the gate of the NMOStransistor NM17. The inverter circuit 15 b outputs a signal qi at itsoutput terminal and the inverter circuit 15 c outputs a signal bqi atits output terminal. These signals qi and bqi are supplied to a unitdelay element 16 i−2 constituting the second delay line 16.

[0071] The unit delay element 16 i is composed of clocked invertercircuits 16 a, 16 b connected in series, inverter circuits 16 c, 16 dconnected in series with the output terminal of the clocked invertercircuit 16 b, an NMOS transistor NM15 which is connected between theoutput terminal of the clocked inverter circuit 16 b and the ground andto whose gate the signal pa is supplied, and a clocked inverter circuit16 f to whose input terminal the signal CLK is supplied and whose outputterminal is connected to the input terminal of the clocked invertercircuit 16 b.

[0072] The clocked inverter circuits 16 a and 16 f are controlled bysignals qi+2 and bqi+2. The clocked inverter circuit 16 b is controlledby the signals pa, bpa. The signal Ri+1 outputted from the unit delayelement 16 i+1 at the (i+1)-th stage is supplied to the input terminalof the clocked inverter circuit 16 a. The clocked inverter circuit 16 boutputs a signal Ri at its output terminal. The inverter circuit 16 coutputs a signal bRi. The signal Ri is supplied to the unit delayelement 16 i−1 and the signal bRi is supplied to the state holdingsection 15 i+2. The inverter circuit 16 d is a dummy inverter circuitcorresponding to the inverter circuit 14 d constituting the unit delayelement 14 i.

[0073]FIG. 3 is a circuit diagram of the unit delay element 14 i shownin FIG. 2A. FIG. 4A is a circuit diagram of the unit delay element 16 ishown in FIG. 2C. In FIGS. 3 and 4A, the same parts as those in FIGS. 2Aand 2C are indicated by the same reference symbols.

[0074] In FIG. 3, the clocked inverter circuit 14 a is composed of PMOStransistors PM2, PM1 and NMOS transistors NM2, NM1 whose current pathsare connected in series between the power supply Vcc and the ground. Theclocked inverter circuit 14 f is composed of PMOS transistors PM4, PM3and NMOS transistors NM4, NM3 whose current paths are connected inseries between the power supply Vcc and the ground. The clocked invertercircuit 14 b is composed of PMOS transistors PM6, PM5 and NMOStransistors NM6, NM5 whose current paths are connected in series betweenthe power supply Vcc and the ground.

[0075] In FIG. 4A, the clocked inverter circuit 16 a is composed of PMOStransistors PM10, PM9 and NMOS transistors NM10, NM9 whose current pathsare connected in series between the power supply Vcc and the ground. Theclocked inverter circuit 16 f is composed of PMOS transistors PM12, PM11and NMOS transistors NM12, NM11 whose current paths are connected inseries between the power supply Vcc and the ground. The clocked invertercircuit 16 b is composed of PMOS transistors PM14, PM13 and NMOStransistors NM14, NM13 whose current paths are connected in seriesbetween the power supply Vcc and the ground.

[0076]FIGS. 2A to 4A show the configuration of the unit delay elements14 i, 16 i, and state holding circuit 15 i at the i-th stage. Each ofthe unit delay elements and state holding circuits at a stage other thanthe i-th stage has the same configuration, with the relationship betweenthe signal input and output being the same as that at the i-th stage.

[0077]FIG. 5 shows the signals at various sections in FIGS. 1 to 4A. Inthe SAD synchronizing circuit of FIG. 1, the input buffer circuit 12generates a signal CLK that lags behind by D1 from the external clockECK with the period T. The signal CLK is delayed for D1+D2 by the delaymonitor 13 and the resulting signal is supplied to the first delay line14. The individual unit delay elements 14 i−3, . . . , 14 i, . . . , 14i+3 constituting the first delay line 14 transfer a signal Din as aforward pulse signal according to the signals p and bp outputted fromthe second signal generator circuit 19.

[0078] Each of the state holding circuits constituting the state holdingsection 15 is set, depending on the signal bpm supplied from the fourthsignal generator circuit 20 and the output signal from the unit delayelement at the preceding stage. Specifically, the state holding circuitsare brought to the set state, when the forward pulse signal passesthrough the first delay line 14.

[0079] When the state holding circuits are in the set state, the unitdelay elements of the second delay line 16 output the backward pulsesignal from the preceding stage to the next stage. When the stateholding circuits are in the reset state, the unit delay elements do notaccept the signal from the preceding stage but propagate the clocksignal CLK supplied in common. Specifically, the second delay line 16transfers a backward pulse signal or clock signal CLK according to thesignals qi+2, bqi+2 supplied from the state holding circuit two stagesahead and the signals pa, bpa supplied from the signal generator circuit18. When the backward pulse signal passes through the second delay line16, the corresponding state holding circuit is brought into the resetstate. The output signal Dout of the second delay line 16 is outputtedvia the output buffer circuit 17, thereby generating an internal clocksignal ICK. As a result, the internal clock signal ICK lags behind fromthe external clock signal ECK as follows:

D1+(D1+D2)+2(T−(D1+D2))+D2=2T

[0080] Consequently, the internal clock signal ICK synchronizes with theexternal clock signal ECK.

[0081] In the SAD synchronizing circuit, synchronization is establishedby the rising of the pulse signal. Therefore, the amount of delay in theunit delay element can be decreased by enhancing the current drivingcapability of the transistor related to the rising of the pulse signal(the transistor that responds when the signal supplied to a circuitchanges from the high to low level). Specifically, in the unit delayelements 14 i, 16 i shown in FIGS. 3 and 4A, the transistors related tothe rising of the pulse signal include the NMOS transistors NM1, NM2,NM3, NM4 and PMOS transistors PM5, PM6 for forward pulses and the NMOStransistors NM9, NM10, NM11, NM12 and PMOS transistors PM13, PM14 forbackward pulses. Thus, the current driving capability can be increasedby widening, for example, the channel width of each of thesetransistors.

[0082] When the ratio of the current driving capability of the NMOStransistors to that of the PMOS transistors is 2:1, the ratio of thechannel width of the former to that of the latter is normally set to1:2. As a result, the current driving capability of the NMOS transistorsis made equal to that of the PMOS transistors. In contrast, in the firstembodiment, the ratio of, for example, the channel width of the NMOStransistors NM1, NM2 to that of the PMOS transistors PM1, PM2 is setequal to or less than, for example, Wn:Wp=1:2 as shown in FIG. 4B. Inaddition, the ratio of the channel width of the PMOS transistors NM5,NM6 to that of the NMOS transistors NM5, NM6 is set equal to or greaterthan, for example, Wn:Wp=1:2 as shown in FIG. 4C.

[0083] Use of this configuration increases the current drivingcapability but permits the gate capacity to increase. The increased gatecapacity can be canceled by making smaller the channel width of each ofthe PMOS transistors PM1, PM2, PM3, PM4, NMOS transistors NM5, NM6, andPMOS transistors PM9, PM10, PM11, PM12, PM13, and PM14 related to thefalling of the pulse signal. As a result, the falling response speed ofthe pulse signal outputted from the clocked inverter circuit gets fasterand the rising response speed of the same pulse signal gets slower thanthe pulse signal inputted to the clocked inverter circuit. This causes aproblem: the pulse width increases each time the pulse passes throughthe unit delay element. However, control is performed so that the pulsesignal from this time on may not be propagated, by causing the signals pand bp to control the clocked inverter circuit 14 b (NM5, NM6, PM5, PM6)and the signals pa, bpa to control the clocked inverter circuit 16 b.This prevents the pulse width from increasing.

[0084] The configuration for changing the current driving capability isnot limited to the case where the channel width is changed. Forinstance, the same configuration can be realized by changing the channellength, the threshold voltage of the transistor, or the substratevoltage.

[0085] As shown in FIG. 4D, when the channel length is changed, forexample, the channel length Lp of the PMOS transistors PM1, PM2 is madelonger than the channel length Ln of the NMOS transistors NM1, NM2.Further, the channel length of the PMOS transistors PM5 and PM6 is madeshorter than that of the NMOS transistors NM5 and NM6.

[0086] When the threshold voltage of the transistor is changed, thethreshold voltage of the NMOS transistor is made lower than usual andthe threshold voltage of the PMOS transistor is made higher than usual.One of the methods of changing the threshold voltage is to control theconcentration of impurities implanted into the channel region.

[0087] When the substrate voltage or well voltage is changed, thebackgating bias of the PMOS transistor is made higher than thebackgating bias of the NMOS transistor.

[0088] This setting makes the rising of the pulse faster.

[0089] With the first embodiment, the current driving capability of thetransistors related to the rising of the pulse signal in each unit delayelement constituting the first and second delay lines 14, 16 (or thetransistors that respond when the signal supplied to a circuit changesfrom the high to low level) is increased. As a result, the rise time ofthe pulse signal can be made shorter, shortening the delay time requiredfor the pulse signal to rise, which improves the accuracy ofsynchronization.

[0090] Furthermore, the clocked inverter circuits in the first andsecond delay elements are controlled by the specific control signals p,bp, pa, bpa, thereby forcing the pulse signal to fall. This prevents thepulse signal with an increased pulse width from being propagated to thenext stage.

[0091] Second Embodiment

[0092] In a second embodiment of the present invention, a case where aninternal clock signal is shifted half the period from an external clocksignal will be explained.

[0093] The second embodiment differs from the first embodiment chieflyin that the amount of delay in the second delay line is made greater bygiving an intermediate potential to the second delay line 16.

[0094]FIG. 6 shows the configuration of a synchronizing circuitaccording to the second embodiment. In FIG. 6, the same parts as thosein the first embodiment are indicated by the same reference symbols. InFIG. 6, a delay monitor 31 has a delay time (2(D1+D2)) of twice the sumof the delay time of the input buffer circuit 12 and that of the outputbuffer circuit 17. The number of unit delay elements of the second delayline 16 is set to half the number of the unit delay elements of thefirst delay line 14. The unit delay elements of the second delay line 16are arranged for every other unit delay element constituting the firstdelay line 14. Specifically, in the synchronizing circuit, a backwardpulse signal advancing along the second delay line 16 is allowed topropagate along as many unit delay elements as equals half the number ofunit delay elements along which the forward pulse advanced along thefirst delay line 14. This causes the internal clock signal to besynchronized with the external clock signal in such a manner that theformer is shifted half the period from the latter.

[0095]FIGS. 7A and 7B schematically show the operation of the stateholding section 15 shown in FIG. 6. In FIGS. 7A and 7B, “S” representsthe set state. When a forward pulse passes through the state holdingsection, it is brought into the set state. In the set state, a unitdelay element for backward pulse signals outputs the backward pulse fromthe preceding stage to the next stage. In addition, “R” indicates thereset state. When a backward pulse passes through the state holdingsection, it is brought into the reset state. With the state holdingsection in the reset state, a unit delay element for backward pulsesignals does not accept the signal from the preceding stage butpropagates the clock signal inputted in common.

[0096] As shown in FIGS. 7A and 7B, in the synchronizing circuit thatachieves synchronization by shifting the internal clock half the period,only half of the information about the setting and resetting of thestate holding circuit is used, which is a waste of information. To avoidthe wasting a pair of adjacent state holding circuits is used to set apiece of information.

[0097] Specifically, as shown in FIGS. 8A, 8B, and 8C, a case where apair of state holding circuits are set is defined as “S”, whereas a casewhere a pair of state holding circuits is reset is defined as “R”. Inaddition, as shown in FIG. 8B, a case where a pair of state holdingcircuits are set and reset is defined as an intermediate state “M”.Namely, the state holding section is designed to have ternaryinformation. In the intermediate state “M,” the amount of delay in aunit delay element constituting the second delay line is halved. Sinceit is difficult to halve the amount of delay in the unit delay elements,the pair of state holding circuits does not accept the input from thepreceding stage but propagates the clock signal CLK inputted in commonin the intermediate state “M” as in the reset “R”. In this case, theamount of delay in the unit delay elements constituting the second delayline 16 is made 1.5 times the amount of delay in the unit delay elementsconstituting the first delay line 14. With this configuration, theaccuracy of synchronization can be improved to half the amount of delayin the unit delay elements, which will be explained later in detail.

[0098]FIG. 9 shows a configuration of FIG. 6. In FIG. 9, the same partsas those in FIGS. 1 and 6 are indicated by the reference symbols andonly the parts differing from FIGS. 1 and 6 will be explained. In thefirst delay line 14, state holding circuit 15, and second delay line 16,two adjacent circuits form a pair. In the second delay line 16, the unitdelay elements 16 i−6, 16 i−4, 16 i−2, 16 i, . . . and the signalgenerator circuits 16 i−5, 16 i−3, 16 i−1, 16 i+1, . . . for controllingthe unit delay elements 16 i−6, 16 i−4, 16 i−2, 16 i, are arrangedalternately.

[0099] A first signal generator circuit 30 is composed of a buffercircuit 30 e with a delay time of D, an inverter circuit 30 a, a delaycircuit 30 b with a delay time of d, an OR circuit 30 c, and an invertercircuit 30 d. The first signal generator circuit 30 generates signals p0and bp0 from the signal delayed by the buffer circuit 30 e for the delaytime D. The pulse width of the signal p0 and bp0 is set almost equal tothe amount of delay in a unit delay element.

[0100]FIG. 10 shows the unit delay elements 14 i, 14 i+1, 16 i, stateholding circuits 15 i, 15 i+1, and signal generator circuit 16 i+1 atthe i-th stage and the (i+1)-th stage of FIG. 9.

[0101] The unit delay element 14 i is composed of a clocked invertercircuit 14 a−1, an inverter circuit 14 b−1 connected in series with theinverter circuit 14 a−1, an inverter circuit 14 d−1 connected in serieswith the output terminal of the inverter circuit 14 b−1, an invertercircuit 14 c−1 connected to the output terminal of the clocked invertercircuit 14 a−1, and a clocked inverter circuit 14 e−1 whose inputterminal is grounded and whose output terminal is connected to the inputterminal of the inverter circuit 14 b−1. The clocked inverter circuits14 a−1, 14 e−1 are controlled by the signals p and bp. The signal Fi−1outputted from the unit delay element 14 i−1 at the (i−1)-th stage issupplied to the input terminal of the clocked inverter circuit 14 a−1.The inverter circuit 14 b−1 outputs a signal Fi at its output terminal.In addition, the inverter circuit 14 c−1 outputs a signal FFi. Thesignals Fi and FFi are supplied to the unit delay elements 14 i+1 andthe state holding circuit 15 i+1, respectively. The inverter circuit 14d−1 is a dummy inverter corresponding to the inverter circuit 16 c−1provided in the unit delay element 16 i explained later.

[0102] The unit delay elements 14 i+1 has almost the same configurationas that of the unit delay element 14 i. The same parts as those in theunit delay elements 14 i are suffixed with “−2” and explanation will beomitted.

[0103] The state holding section 15 i is composed of a clocked invertercircuit 15 a−1 and an inverter circuit 15 b−1 connected in series. Theclocked inverter circuit 15 a−1 is composed of PMOS transistors PM30,PM29 and NMOS transistors NM30, NM29 connected in series between a powersupply Vcc and the ground. The signal bRi−6 outputted from the unitdelay element 16 i+−6 at the (i−6)-th stage constituting the seconddelay line 16 is supplied to the gate of the PMOS transistor PM30. Thesignal bpm is supplied to the gates of the PMOS transistor PM29 and theNMOS transistor NM30. The signal FFi−1 supplied from the unit delayelement 14 i−1 at the (i−1)-th stage constituting the first delay line14 is supplied to the gate of the NMOS transistor NM29. The invertercircuit 15 b−1 outputs a signal qi at its output terminal.

[0104] The state holding circuit 15 i+1 has almost the sameconfiguration as that of the state holding circuit 15 i. The same partsas those in the state holding circuit 15 i are suffixed with “−2” andexplanation will be omitted.

[0105] The unit delay element 16 i is composed of a clocked invertercircuit 16 a−1, an inverter circuit 16 b−1 connected in series with theclocked inverter circuit 16 a−1, an inverter circuit 16 c−1 connected tothe output terminal of the inverter circuit 16 b−1, a clocked invertercircuit 16 d−1 to whose input terminal the signal CLK is supplied andwhose output terminal is connected to the input terminal of the invertercircuit 16 b−1, an inverter circuit 16 e−1 connected to the outputterminal of the clocked inverter circuit 16 a−1, and a PMOS transistorPM31 and an NMOS transistor NM31 whose current paths are connected inseries.

[0106] The PMOS transistor PM31 and NMOS transistor NM31 output a signalbqqi+5 according to the signal qqi+5 supplied from the signal generatorcircuit at the (i+5)-th stage (not shown). The clocked inverter circuit16 a−1 is controlled by the signals bqqi+5, qqi+5 and the clockedinverter circuit 16 d−1 is controlled by the signals qqi+5, bqqi+5. Thesignal Ri+2 outputted from the unit delay element at the (i+2)-th stage(not shown) is supplied to the input terminal of the clocked invertercircuit 16 a−1. The inverter circuit 16 b−1 outputs a signal Ri at itsoutput terminal. In addition, the inverter circuit 16 c−1 outputs asignal bRi. The inverter circuit 16 e−1 is a dummy inverter circuitcorresponding to the inverter circuit 14 c−1 constituting the unit delayelement 14 i.

[0107] The signal controlling the PMOS transistor PM31, NMOS transistorNM31, and clocked inverter circuit 16 d−1 is not limited to the outputsignal of the signal generator circuit at the (i+5)-th stage. The outputsignal of the signal generator circuit at another stage may be usedinstead.

[0108] The signal generator circuit 16 i+1 is composed of PMOStransistors PM36, PM37 and NMOS transistors NM37, NM36 connected inseries between the power supply Vcc and the ground and PMOS transistorsPM38, PM39 whose current paths are connected in series with theconnection node of the PMOS transistors PM36, PM37.

[0109] The output signal qi of the state holding circuit 15 i issupplied to the gates of the PMOS transistor PM36 and NMOS transistorNM36. The output signal qi+1 of the state holding circuit 15 i+1 issupplied to the gates of the PMOS transistor PM37 and NMOS transistorNM37. The signal pb0 outputted from the first signal generator circuit30 is supplied to the gate of the PMOS transistor PM39, to one end ofwhose current path a voltage VBL is applied. In addition, the signal bqiis supplied to the gate of the PMOS transistor PM38. A signal bqqi+1 isoutputted at the connection node of the PMOS transistor PM37 and NMOStransistor NM37. The signal bqqi+1 is supplied to the unit delay element16 i−4.

[0110]FIG. 11 is a circuit diagram of the unit delay elements 14 i, 14i+1. FIG. 12 is a circuit diagram of the unit delay elements 16 i and 16i+1. In FIGS. 11 and 12, the same parts as those in FIG. 10 areindicated by the same reference symbols.

[0111] In the above configuration, when both of the output signals qiand qi+1 of the adjacent state holding circuits 15 i and 15 i+1 are atthe high level, or when a pair of state holding circuits are in the setstate, the output signal bqqi+1 of the signal generator circuit 16 i+1goes low. When both of the output signals qi and qi+1 are at the lowlevel, or when a pair of state holding circuits are in the reset state,the output signal bqqi+1 of the signal generator circuit 16 i+1 goeshigh. Furthermore, when the signal qi of the outputs of a pair of stateholding circuits is at the high level, the signal qi+1 is at the lowlevel, and the output signal bp0 of the first signal generator circuit30 is at the low level, or when the pair are in the intermediate state“M,” the output signal bqqi+1 of the signal generator circuit 16 i+1 isbrought to the level of voltage VBL.

[0112] The output signal bqqi+5 of the signal generator circuit at the(i+5)-th stage (not shown) supplied to the unit delay element 16 i isset high or low, depending on the output signal of the state holdingcircuits at the (i+4)-th stage and the (i+5)-th stage as describedabove.

[0113] In the unit delay element 16 i, the clocked inverter circuit 16a−1 and inverter circuit 16 b−1 form a path, when the pair of stateholding circuits are in the set state. The backward pulse signalsupplied from the preceding stage is propagated via the path to the nextstage.

[0114] When the pair of state holding circuits are in the reset state,the clocked inverter circuit 16 a−1 is made nonconducting and theclocked inverter circuit 16 d−1 is made conducting. As a result, thebackward pulse signal from the preceding stage is cut off and the clocksignal CLK is transferred to a subsequent stage.

[0115] On the other hand, as described above, in the intermediate state“M,” the signal qi of the output signals of the pair of state holdingcircuits is at the high level, the signal qi+1 is at the low level, andthe output bp0 of the first signal generator circuit 30 is at the lowlevel. At this time, the output signal bqqi+1 of the signal generatorcircuit 16 i+1 is at the level of voltage VBL. The voltage VBL is apotential that lowers the current driving capability of the NMOStransistor of the clocked inverter circuit 16 d−1 allowing the clocksignal CLK to pass through. The voltage VBL is set at about 1.0 V, whenthe potential of the signal bqi+1 is set at, for example, 1.8 V in thereset state and at 0 V in the set state. By setting the voltage VBL thisway, the clock signal is delayed 1.5 times the amount of delay in theclock signal CLK in the reset state.

[0116] As shown in FIG. 13, the signal bp0 is a signal that fallsimmediately before the clock signal CLK rises and rises immediatelyafter the clock signal CLK rises. Specifically, the pulse width of thesignal bp0 is set to a value corresponding to about the amount of delayin a unit delay element. As a result, the signal bqqi+1(bqqi+5) is atthe voltage VBL, only when the signal bp0 is at the low level.

[0117] Specifically, as the forward pulse signal is propagated along thefirst delay line 14, the output signals of a pair of adjacent stateholding circuits often go high and low. As shown in FIG. 14A, however,in a case where the output signals qi, qi+1 of a pair of adjacent stateholding circuits both go high or low, when the signal bp0 is notgenerated, the intermediate state “M” will not appear.

[0118] In contrast, as shown in FIG. 14B, when the output signals qi,qi+1 of a pair of adjacent state holding circuits go high and lowrespectively and the signal bp0 is generated, the intermediate state “M”appears.

[0119] When the pair of state holding circuits are in the intermediatestate “M” where the holding circuits are in the set state and the resetstate, the clocked signal CLK is delayed 1.5 times the amount of usualdelay. As a result, the signal Dout outputted from the second delay line16 is outputted (T−2(D1+D2))/2 later than the signal Din supplied to thefirst delay line 14 (as shown in FIG. 13). Furthermore, the signal Doutis delayed by the output buffer circuit 17 for the amount of delay D2.As a result, the internal clock signal ICK is delayed half the periodfrom the external clock signal ECK.

[0120] With the second embodiment, in the intermediate state “M” where apair of state holding circuits are in the set state and the reset state,the delay time of the unit delay element is made 1.5 times the amount ofusual delay by decreasing the driving capability of the NMOS transistorconstituting the clocked inverter circuit 16 d−1 to which the clocksignal CLK is supplied. As a result, the accuracy of synchronization canbe improved to half the amount of delay in a unit delay element, whichmakes it possible to generate an internal clock signal ICK delayed halfthe period from the external clock signal ECK.

[0121] FIGS. 15 to 17 show a modification of the second embodiment. InFIGS. 15 to 17, the same parts as those in FIGS. 9 to 12 are indicatedby the same reference symbols. The configuration of the state holdingsection 15 and the second delay line 16 in FIGS. 15 to 17 differs fromthat of FIGS. 9 to 12.

[0122] Specifically, in the state holding circuit 15 i shown in FIG. 16,the inverter 15 c−1 is connected in series with the output terminal ofthe inverter circuit 15 b−1. The inverter circuit 15 c−1 outputs asignal bqi at its output terminal. Similarly, in the state holdingcircuit 15 i+1, the inverter 15 c−2 is connected in series with theoutput terminal of the inverter circuit 15 b−2. The inverter circuit 15c−2 outputs a signal bqi+1 at its output terminal.

[0123] As shown in FIGS. 16 and 17, in the unit delay element 16 iconstituting the second delay line, the clocked inverter circuit 16 a−1is controlled by the signals bqi+1, qi+1. In addition, the signals qi+1,qi are supplied to the input terminals of the NOR circuit 16 f−1. Theclocked inverter circuit 16 d−1 is controlled by the signals qi+1 andthe output signal of the NOR circuit 16 f−1.

[0124] Furthermore, the signal generator circuit 16 i+1 has a clockedinverter circuit 16 g. The clocked inverter circuit 16 g is composed ofPMOS transistors PM41, PM42, PM43, PM44 and NMOS transistors NM41, NM42,MN43, NM44 connected in series between the power supply Vcc and theground. The clock signal CLK is supplied to the gates of the PMOStransistor PM41 and NMOS transistor NM44. The signals bqi and qi aresupplied to the gates of the PMOS transistor PM42 and NMOS transistorNM43, respectively. In addition, the signals qi+1 and bqi+1 are suppliedto the gates of the PMOS transistor PM43 and NMOS transistor NM42,respectively. The signals bq0 and p0 are supplied to the gates of thePMOS transistor PM44 and NMOS transistor NM41, respectively. Theconnection node of the PMOS transistor PM44 and NMOS transistor NM41 isconnected to the output terminals of the clocked inverter circuits 16a−1 and 16 d−1.

[0125] When the output signals qi and qi+1 of a pair of adjacent stateholding circuits 15 i and 15 i+1 are both at the high level, or whenthey are in the set state, the clocked inverter circuit 16 a−1 of theunit delay element 16 i is made conducting and the clocked invertercircuits 16 d−1 and 16 g are made nonconducting. This enables thebackward pulse signal Ri+2 outputted from the unit delay element at thepreceding stage to propagate through the clocked inverter circuit 16 a−1and inverter circuit 16 b−1.

[0126] When the output signals qi and qi+1 of the pair of adjacent stateholding circuits 15 i and 15 i+1 are both at the low level, or when theyare in the reset state, the clocked inverter circuit 16 d−1 of the unitdelay element 16 i is made conducting and the clocked inverter circuits16 a−1 and 16 g are made nonconducting. As a result, the clock signalCLK is propagated via the clocked inverter circuit 16 d−1 and invertercircuit 16 b−1 to a subsequent stage.

[0127] When the output signal qi of the pair of adjacent state holdingcircuits 15 i and 15 i+1 is at the high level and the output signal qi+1is at the low level, and the output signal bp0 of the first signalgenerator circuit 30 is at the low level, the pair are in theintermediate state. In the intermediate state, both of the clockedinverter circuits 16 a−1 and 16 d−1 are made nonconducting and theclocked inverter circuit 16 g is made conducting. As a result, the clocksignal CLK is propagated via the clocked inverter circuit 16 g andinverter circuit 16 b−1 to a subsequent stage. The amount of delay inthe clock signal CLK passing through the clocked inverter circuit 16 gis set 1.5 times as large as the amount of delay required to passthrough the clocked inverter circuit 16 a−1 or the amount of delayrequired to pass through the clocked inverter circuit 16 d−1. With thesetting means, at least one of, for example, the channel width andchannel length of the NMOS transistor and PMOS transistor constitutingthe clocked inverter circuit 16 g, the threshold voltages of thesetransistors, and the voltage of the substrate at which the transistorsare formed is changed. In this way, the current driving capability ofthe NMOS transistor is lowered.

[0128] For example, when the channel width is changed, the channel widthof the NMOS transistor is made narrower than the ordinary size. When thechannel length is changed, the channel length of the NMOS transistor ismade greater than the channel length of the PMOS transistor. When thethreshold voltage of the transistor is changed, the threshold voltage ofthe NMOS transistor is made higher than usual and the threshold voltageof the PMOS transistor is made lower than usual. When the substratevoltage is changed, the backgating bias of the NMOS transistor is madehigher than the backgating bias of the PMOS transistor.

[0129] When the amount of delay in the clocked inverter circuit 16 gitself is equal to or more than 1.5 times that in a unit delay element,the signal one stage of inverter circuit before the clock signal CLKsupplied to the clocked inverter circuit 16 d−1 is used as the clocksignal CLK supplied to the clocked inverter circuit 16 g. Depending onthe situation, the signal two stages of inverter circuit before theclock signal CLK may be used instead. Specifically, the clock signalwith earlier timing than that of the clock signal CLK supplied to theclocked inverter circuit 16 d−1 may be used.

[0130] Furthermore, the sizes, threshold voltages, and substratevoltages of the PMOS transistors and NMOS transistors constituting theclocked inverter circuit 16 g may be combined with the location at whichthe inverted clock signal bCLK is drawn out.

[0131] With the above configuration, in the intermediate state “M” wherea pair of state holding circuits are in the set state and in the resetstate, the clocked inverter circuit 16 g transfers the clock signal CLK.By lowering the driving capability of the NMOS transistors constitutingthe clocked inverter circuit 16 g, the delay time of the unit delayelement is made 1.5 times the amount of usual delay. As a result, theaccuracy of synchronization can be improved to half the amount of delayin the unit delay element, which makes it possible to generate aninternal clock signal ICK delayed half the period from the externalclock signal ECK.

[0132] While in the second embodiment, the case where the amount ofdelay in the second delay line is made 1.5 times the amount of usualdelay, it goes without saying that the amount of delay in the seconddelay line may be set to a value other than 1.5 times.

[0133] Third Embodiment

[0134] In the second embodiment, the accuracy of synchronization can beimproved to half the amount of delay in a unit delay element. Theinternal clock signal synchronized with the external clock signal isshifted half the period from the external clock signal. In a thirdembodiment of the present invention, a circuit which has half the amountof delay in a unit delay element (that is, half the accuracy ofsynchronization) and whose clock signal has the same phase and period asthose of an external clock signal will be explained.

[0135]FIG. 18 shows the third embodiment of the present invention. InFIG. 18, the same parts as those in FIG. 15 are indicated by the samereference symbols. FIG. 19 shows the signals at various sections of FIG.18. In FIG. 18, a double period signal generator circuit 51 a generatessignals WECK and bWECK which have twice the period of an external clocksignal ECK. The signal WECK, together with the external clock signalECK, is supplied to a NAND 52 a. The signal bWECK, together with theexternal clock signal ECK, is supplied to a NAND 52 b. The outputsignals of the NAND circuits 52 a and 52 b are supplied to invertercircuits 53 a and 53 b respectively. The output signals ECKa and ECKb ofthe inverter circuits 53 a and 53 b are clock signals separated into oddand even clock signals according to the signals WECK and bWECK. Thesignals ECKa and ECKb are supplied to input buffer circuits 12 a and 12b with the amount of delay D1, respectively.

[0136] The odd and even clock signals CLKa and CLKb outputted from theinput buffer circuits 12 a and 12 b are combined via a NOR circuit 54and an inverter circuit 55. The resulting signal is supplied to oneinput terminal of a NAND circuit 56. A power supply voltage Vcc issupplied to the other input terminal of the NAND circuit 56. The outputsignal of the NAND circuit 56 is supplied to an inverter circuit 57. Theoutput signal CLKab of the inverter circuit 57 is supplied to a delaymonitor 31.

[0137] On the other hand, the double-period signal generator circuit 51b generates signals WDin and bWDin with twice the period of the externalclock signal ECK as shown in FIG. 19. The signal WDin, together with thesignal Dinab with a delay time of 2(D1+D2) outputted from the delaymonitor 31, is supplied to a NAND circuit 58 a. The signal bWDin,together with the output signal Dinab of the delay monitor 31, issupplied to a NAND circuit 58 b. The output signals from the NANDcircuits 58 a and 58 b are supplied via inverter circuits 59 a and 59 bto one input terminal of each of NOR circuits 60 a and 60 b,respectively. The other input terminals of the NOR circuits 60 a and 60b are grounded. The output terminals of the NOR circuits 60 a and 60 bare connected to inverter circuits 61 a and 61 b respectively. Theoutput signals Dina and Dinb of the inverter circuits 61 a and 61 b areobtained by separating the output signal Dinab of the delay monitor 31into odd and even signals according to the signal WDin and bWDin. Thesignals Dina and Dinb, together with the odd and even clock signals CLKaand CLKb outputted from the input buffer circuits 12 a and 12 b, aresupplied to half STBD (Synchronous Traced Backward Delay) 62 a and 62 b.The half STBD 62 a, and half STBD 62 b have the same configuration asthat of the circuit shown in FIG. 15. Specifically, the second delayline for backward pulses is made half the length of the first delay linefor forward pulses. The state holding section has three states: a setstate, a reset state, and an intermediate state. The odd and evensignals Douta and Doutb outputted from the half STBD 62 a, and half 62 bare combined via a NOR circuit 63 and an inverter circuit 64. Theresultant output signal Doutab outputted from the inverter circuit 64 issupplied to an output buffer circuit 17 with a delay time of D2. Theoutput buffer circuit 17 outputs an internal clock signal ICK. Theinternal clock signal ICK synchronizes with the external clock signalECK and has the period coinciding with the external clock signal ECK.

[0138] With the third embodiment, the external clock signal is dividedinto an odd clock signal and an even clock signal. The odd and evenclock signals are shifted half the period from the external clock signaland each synchronized with the external clock independently. Then, theodd and even signal shifted half the period from and synchronized withthe external clock signal are combined. As a result, the accuracy ofsynchronization can be improved to half the amount of delay in the unitdelay element. In addition, an internal clock signal ICK synchronizingwith the external clock signal can be generated.

[0139] Furthermore, when the external clock signal is divided into anodd clock signal and an even clock signal and the odd and even clocksignals are shifted half the period from the external clock signal andeach synchronized with the external clock signal independently, a seriesconnection of the odd clock circuit and the even clock circuit can beconsidered. In this case, there is a possibility that phase shift willbe amplified. By connecting the odd clock circuit and the even clockcircuit in parallel as shown in the third embodiment, the amplificationof the phase shift can be prevented.

[0140] Fourth Embodiment

[0141] Hereinafter, a fourth embodiment of the present invention will beexplained. In the second and third embodiments, the state holdingsection has three states: the set state, reset state, and intermediatestate. This enables the internal clock signal to be shifted half theperiod from and synchronized with the external clock signal. In thefourth embodiment, a circuit which shifts the internal clock signalone-fourth the period from the external clock signal and synchronizesthe resulting signal with the external clock signal will be explained.

[0142]FIGS. 20A to 20E show a state holding section according to thefourth embodiment of the present invention. In the fourth embodimentfour adjacent state holding circuits make one set, which enables thesetting of five states. Specifically, as shown by 15 i in FIG. 20A, whenall the four state holding circuits are reset, they are defined as beingin the reset state “R”. As shown by 15 i in FIG. 20E, when all the fourstate holding circuits are set, they are defined as being in the setstate “S”. As shown by 15 i in FIG. 20B, when, of the four state holdingcircuits, one is set and the remaining three are reset, they are definedas being in a first intermediate state “M1”. As shown by 15 i in FIG.20C, when, of the four state holding circuits, two are set and theremaining two are reset, they are defined as being in a secondintermediate state “M2”. As shown by 15 i in FIG. 20D, when, of the fourstate holding circuits, three are set and the remaining one is reset,they are defined as being in a third intermediate state “M3”.

[0143] FIGS. 21 to 25 show part of the first delay line 14, stateholding section 15, and second delay line 16 related to the fourthembodiment. In FIGS. 21 to 25, the same parts as those in the first tothird embodiments are indicated by the same reference symbols.

[0144] As shown in FIG. 21, four state holding circuits make a set inthe state holding section 15. In the second delay line 16, one unitdelay element 16 i+1 is allocated to four state holding circuits 15 i+1to 15 i+4.

[0145]FIG. 22 shows unit delay elements 14 i+1 and 14 i+2 constitutingthe first delay line 14 FIG. 23 shows unit delay elements 14 i+3 and 14i+4 constituting the first delay line 14. The unit delay elements 14 i+1to 14 i+4 have the same configuration. The output signal of a unit delayelement at the preceding stage is inputted to a unit delay element and astate holding circuit at a subsequent stage.

[0146] The unit delay element 14 i+1 is composed of inverter circuits 71a, 72 a, 73 a, 74 a, 75 a, 76 a, and 77 a. The output signal Fi of theunit delay element 14 i at the preceding stage is supplied to theinverter circuit 71 a. The inverter circuit 72 a has its input terminalgrounded and its output terminal connected to the output terminal of theinverter circuit 71 a. The inverter circuit 73 a has its input terminalconnected to the output terminals of the inverter circuits 71 a and 72 aand outputs a signal Fi+1 at its output terminal. The inverter circuit74 a has its input terminal connected to the output terminals of theinverter circuits 71 a and 72 a and outputs a signal FFi+1 at its outputterminal. The inverter circuits 75 a, 76 a, and 77 a are dummy invertercircuits corresponding to the signal generator circuit connected to theunit delay element constituting the second delay line, which will beexplained later.

[0147] In the unit delay elements 14 i+2 to 14 i+4, the same parts asthose of the unit delay element 14 i+1 are suffixed with “b,” “c,” and“d,” and explanation of them will be omitted.

[0148]FIG. 24 shows the configuration of the state holding circuits 15i+1 to 15 i+4. The state holding circuits 15 i+1 to 15 i+4 have the sameconfiguration. Each of the state holding circuits 15 i+1 to 15 i+4 iscomposed of clocked inverter circuits 81 a, 81 b, 81 c, and 81 dcontrolled according to a signal bpm and inverter circuits 82 a, 82 b,82 c, and 82 d connected to the output terminals of the clocked invertercircuits 81 a to 81 d, respectively. Each of the state holding circuits15 i+1 to 15 i+4 is set according to the output signals FFi to FFi+3 ofthe unit delay elements 14 i to 14 i+3 constituting the first delay line14 and reset according to the output signal of the unit delay element 16i−3 (not shown) constituting the second delay line 16. The state holdingcircuits 15 i+1 to 15 i+4 output signals qi+1 to qi+4, respectively.

[0149]FIG. 25 shows a unit delay element 16 i+1 constituting the seconddelay line 16. The unit delay element 16 i+1 is composed of clockedinverter circuits 91 and 92, inverter circuits 93 and 94 and a NORcircuit 95. The signal Ri+5 outputted from the unit delay element 16 i+5(not shown) at the preceding stage is inputted to the input terminal ofthe clocked inverter circuit 91. The clock signal CLK is supplied to theinput terminal of the clocked inverter circuit 92. The inverter circuit93 has its input terminal connected to the output terminals of theclocked inverter circuits 91 and 92 and outputs a signal Ri+1 at itsoutput terminal. The inverter circuit 94 receives a signal qi+3 and hasits output terminal connected to the clocked inverter circuit 91. TheNOR circuit 95 receives signals qi, qi+1 and qi+2 and has its outputterminal connected to the clocked inverter circuit 92.

[0150] The clocked inverter circuit 91 is controlled by the outputsignal qi+3 of the state holding circuit 15 i+3 and the signal bqi+3inverted by the inverter circuit 94. The output signals qi, qi+1 andqi+2 of the state holding circuits 15 i, 15 i+1 and 15 i+2 are suppliedto the NOR circuit 95. The clocked inverter circuit 92 is controlled bythe output signal of the NOR circuit 95 and the output signal qi+3 ofthe state holding circuit 15 i+3.

[0151] Signal generator circuits 16 i+2, 16 i+3 and 16 i+4 are connectedto the input terminal of the inverter circuit 93. Each of the signalgenerator circuits 16 i+2, 16 i+3 and 16 i+4 is composed of invertercircuits 96 a, 96 b and 96 c to which a clock signal bCLK with earliertiming than the clock signal CLK is supplied and clocked invertercircuits 97 a, 97 b and 97 c to which the clock signals CLK outputtedfrom the inverter circuits 96 a, 96 b and 96 c are supplied.

[0152] In the clocked inverter circuit 97 a, the PMOS transistors arecontrolled by signals CLK, bqi, qi+1, qi+2, qi+3 and bp0 and the NMOStransistors are controlled by signals CLK, qi, bqi+1, bqi+2, bqi+3 andp0.

[0153] In the clocked inverter circuit 97 b, the PMOS transistors arecontrolled by signals CLK, bqi, bqi+1, qi+2, qi+3 and bp0 and the NMOStransistors are controlled by signals CLK, qi, qi+1, bqi+2, bqi+3 andp0.

[0154] In the clocked inverter circuit 97 c, the PMOS transistors arecontrolled by signals CLK, bqi, bqi+1, bqi+2, qi+3 and bp0 and the NMOStransistors are controlled by signals CLK, qi, qi+1, qi+2, bqi+3 and p0.

[0155] In the above configuration, when the state holding section is inthe set state, all the output signals qi, qi+1, qi+2 and qi+3 of thefour adjacent state holding circuits 15 i, 15 i+1, 15 i+2 and 15 i+3 areat the high level. At this time, in the unit delay element 16 i+1 of thesecond delay line 16, the clocked inverter circuit 91 is made conductingand the clocked inverter circuits 92, 96 a, 96 b and 96 c are madenonconducting. This allows the output signal Ri+5 of the unit delayelement at the preceding stage to pass through.

[0156] On the other hand, when the state holding section is in the resetstate, all the output signals qi, qi+1, qi+2 and qi+3 of the fouradjacent state holding circuits 15 i, 15 i+1, 15 i+2 and 15 i+3 are atthe low level. At this time, in the unit delay element 16 i+1, theclocked inverter circuits 91, 96 a, 96 b and 96 c are made nonconductingand the clocked inverter circuit 92 is made conducting. This allows theclock signal CLK to pass through.

[0157] When the state holding section is in the first intermediate state“M1,” the signal qi is high and the signals qi+1, qi+2 and qi+3 are low.At this time, the clocked inverter circuit 97 a is conducting, formingsuch a path as has 1.25 times the amount of delay in a unit delayelement from the rising of the clock signal CLK.

[0158] When the state holding section is in the second intermediatestate “M2,” the signals qi and qi+1 are high and the signals qi+2 andqi+3 are low. At this time, the clocked inverter circuit 97 b isconducting, forming such a path as has 1.5 times the amount of delay ina unit delay element from the rising of the clock signal CLK.

[0159] When the state holding section is in the third intermediate state“M3,” the signals qi, qi+1 and qi+2 are high and the signal qi+3 is low.At this time, the clocked inverter circuit 97 c is conducting, formingsuch a path as has 1.75 times the amount of delay in a unit delayelement from the rising of the clock signal CLK.

[0160] Specifically, the amount of delay in the clocked invertercircuits 97 a, 97 b and 97 c is set to 1+m/4 (m=1, 2, 3) times theamount of delay in the clocked inverter circuits 91 and 92.

[0161] As described above, 1.25 times, 1.5 times, and 1.75 times theamount of delay in a unit delay element can be realized by changing thechannel width of the NMOS transistors and PMOS transistors constitutingthe clocked inverter circuits to decrease the current drivingcapability. Alternately, they can be realized by using the signal bbCLKone stage of inverter circuit before the signal bCLK as the input signalto the signal generator circuits 16 i+2, 16 i+3 and 16 i+4.

[0162] With the fourth embodiment, since the internal clock signal canbe synchronized with the external clock signal with an accuracy ofone-fourth the amount of delay in a unit delay element, the accuracy ofsynchronization can be improved much more.

[0163] Fifth Embodiment

[0164] With the forth embodiment, the accuracy of synchronization can beimproved to one-fourth the amount of delay in a unit delay element. Thesynchronized internal clock signal, however, is shifted one-fourth ofthe period from the external clock signal. In a fifth embodiment of thepresent invention, a circuit for generating an internal clock signalsynchronizing with the external clock by combining four units of thesynchronizing circuit of the fourth embodiment in parallel will beexplained.

[0165]FIG. 26 shows a synchronizing circuit according to the fifthembodiment and FIG. 27 shows the signals at various sections in FIG. 26.The synchronizing circuit is basically the same as the circuit shown inFIG. 18. The external clock signal ECK is divided into four clocksignals. Each clock signal is shifted one-fourth of the periodindependently. The resulting clock signals shifted one-fourth of theperiod from each other are combined by a NOR circuit, which therebygenerates an internal clock signal ICK.

[0166] Specifically, the external clock signal ECK is supplied to fourNAND circuits 101 a to 101 d. The signals (a, b, c, d) supplied fromdouble-period signal generator circuits 103 and 104 are supplied to theNAND circuits 101 a to 101 d. The output signals of the NAND circuits101 a to 101 d are supplied to inverter circuits 102 a to 102 d. Theoutput signals (e, f, g, h) of the inverter circuits 102 a to 102 d aresupplied to input buffer circuits 12 a to 12 d. The output signals (i,j, k, l where j, k, l are not shown in FIG. 27) of the input buffercircuits 12 a to 12 d are supplied to a NOR circuit 105 and then to aninverter circuit 106, with the result that they are combined. The outputsignal (m) of the inverter circuit 106 passes through NOR circuits 107 ato 107 c, inverter circuits 108 a to 108 c, NAND circuits 109 a to 109c, and inverter circuits 110 a to 110 c and is supplied to a delaymonitor 31.

[0167] The output signal (n) of the delay monitor 31 is supplied to NANDcircuits 113 a to 113 d. The signals (o, p, q, r) supplied from thedouble-period signal generator circuits 111 and 112 are supplied to theNAND circuits 113 a to 113 d. The output signals of the NAND circuits113 a to 113 d are supplied via inverter circuits 114 a to 114 d toquarters STBD 115 a to STBD 115 d. The output signal (s) of the invertercircuit 114 a is as shown in FIG. 27. The output signals of the otherinverter circuits 114 b to 114 d are delayed for half the clock of thesignal (n) from the signal (s) in sequence. The signals supplied fromthe input buffer circuits 12 a to 12 d are supplied to the quarters STBD115 a to STBD 115 d, respectively. As shown in FIGS. 21 to 25, in thequarters STBD 115 a to STBD 115 d, the second delay line for backwardpulses is made one-fourth the first delay line for forward pulses. Thestate holding section has five states: the set state, the reset state,and a first to a third intermediate state. The output signals (w, t, u,v, where t, u, v are not shown in FIG. 27) of the quarters STBD 115 a toSTBD 115 d are supplied to a NOR circuit 116 and then to an invertercircuit 117, with result that they are combined. The output signal (x)of the inverter circuit 117 is supplied to an output buffer circuit 17with delay time of D2. The output buffer circuit 17 outputs an internalclock signal ICK at its output terminal. The internal clock signal ICKhas the same period as that of the external clock signal ECK and is insynchronization with the external clock signal ECK.

[0168] With the fifth embodiment, because the internal clock signal issynchronized with the external clock signal with an accuracy ofone-fourth the amount of delay in a unit delay element, the accuracy ofsynchronization is improved. Moreover, an internal clock signal ICK withthe same period of the external clock ECK can be generated.

[0169] In the fourth and fifth embodiments, the circuits for improvingthe accuracy of synchronization and synchronizing the internal clocksignal with the external clock signal have been explained. The essenceof the fourth and fifth embodiments is that the high-frequency clocksignal is divided into low-frequency clock signals and each of thelow-frequency clock signals is synchronized with the high-frequencyclock signal. Finally, the low-frequency clock signals are combined byan OR circuit (or a NOR circuit) to restore the high-frequency clocksignal.

[0170] In the first to third embodiments, use of a single synchronizingcircuit limits the frequency band. Since the input buffer circuits andoutput buffer circuits have delay particularly in a high-frequency band,the single synchronizing circuit can deal with a maximum of about 300MHz. However, use of the circuits shown in the fourth and fifthembodiments theoretically removes a limit on the frequency.

[0171] Sixth Embodiment

[0172] Hereinafter, means for making constant the pulse width of thesignal supplied to the unit delay elements constituting a delay line andthe pulse width of the signal outputted from the unit delay elementswill be explained.

[0173] Generally, when the size of an NMOS transistor is equal to thatof a PMOS transistor, the NMOS transistor has a higher current drivingcapability than that of the PMOS transistor. When the ratio of thecurrent driving capability of the NMOS transistor to that of the PMOStransistor in a CMOS inverter circuit is 2:1 and the NMOS and PMOStransistors have the same channel length, the ratio of the channel widthof the NMOS transistor to that of the PMOS transistor is generally setto 1:2 to equalize the logical threshold values, thereby causing therising time of the pulse signal to coincide with its falling time.

[0174] In the case of a NOR circuit where the ratio of the currentdriving capability of the NMOS transistor to that of the PMOS transistoris 2:1, when the logical threshold values are equalized, the ratio ofthe channel width of the NMOS transistor to that of the PMOS transistoris 1:4. Similarly, in the case of a NAND circuit, the channel widthratio is 1:1.

[0175] For example, a unit delay element includes a NOR circuit whoselogical threshold values are equalized. Although the pulse widths of thetwo input signals to the NOR circuit are the same, the pulse width willchange because of the logic of the NOR circuit, when one pulse is laterin timing than the other pulse.

[0176]FIG. 28 shows an example of a unit delay element composed of aclocked inverter circuit and a NOR circuit. Unit delay elements 14 i and14 i+1 connected in series are composed of clocked inverter circuits 201a and 202 a and NOR circuits 201 b and 202 b. The clocked invertercircuit 201 a is composed of PMOS transistors MP1 and MP2 and NMOStransistors MN2 and MN1. The clocked inverter circuit 202 a is composedof PMOS transistors MP4 and MP3 and NMOS transistors MN4 and MN3. Theoutput signal from the clocked inverter circuit 201 a in the unit delayelement 14 i and the signal bFi−1 outputted from the clocked invertercircuit in the unit delay element at the preceding stage are supplied tothe input terminals of the NOR circuits 201 b. Similarly, the outputsignal from the clocked inverter circuit 202 a in the unit delay element14 i+1 and the signal bFi outputted from the clocked inverter circuit201 a in the unit delay element 14 i at the preceding stage are suppliedto the input terminals of the NOR circuits 202 b.

[0177]FIG. 29 shows the signals at various sections in FIG. 28. First, acase where a pulse signal Fi−1 with a pulse width of T is supplied tothe input terminal of the clocked inverter circuit 201 a will beconsidered. It is assumed that the amount of delay in the falling of thepulse signal Fi at the NMOS transistor and the amount of delay in therising of the pulse signal at the PMOS transistor in the clockedinverter circuit 201 a are both “d”. Because the logical thresholdvalues are equalized in the clocked inverter circuit 201 a, the amountof delay in the rising and that in the falling are equal. The pulsesignal bFi outputted at the output terminal of the clocked invertercircuit 201 a is an inverted pulse delayed the amount of delay “d” fromthe input pulse signal Fi−1. At this time, the pulse width remainsunchanged at T.

[0178] The signal bFi−1 inputted to the NOR circuit 201 b is a signalone stage of unit delay element ahead. Therefore, the signal bFi has thesame pulse width T as that of the signal bFi−1 but is delayed for adelay time of d+D from the signal bFi−1. The letter “D” is the amount ofdelay in both of the rising and falling of the NOR circuit 201 b.Because the logical threshold values in the NOR circuit 201 b areequalized, the amount of delay in the rising and that in the falling areequal.

[0179] The rising of the signal Fi outputted from the NOR circuit 201 bis determined by the signal bFi falling later than the signal bFi−1 andlags behind by the amount of delay “D” from the falling of the signalbFi. Similarly, since the falling of the signal Fi is determined by thesignal bFi−1 rising earlier and lags behind by the amount of delay “D”from the rising of the signal bFi−1, it is equal to the falling of therising of the signal Fi−1. The pulse width of the signal Fi is T−(d+D).

[0180] The signal Fi is supplied to the clocked inverter circuit 202 ain the unit delay element 14 i+1. Thus, the rising and falling of theoutput signal bFi+1 of the clocked inverter circuit 202 b both lagbehind by the amount of delay “d”. The pulse width of the signal bFi+1is T−(d+D).

[0181] The rising of the output signal Fi+1 of the NOR circuit 202 b towhich the signal bFi+1 and the signal bFi are supplied is determined bythe falling of the signal bFi+1 and lags behind by the amount of delay“D” from the signal bFi+1. The falling of the signal Fi+1 lags behind bythe amount of delay “D” from the rising of the signal bFi rising withthe same timing as that of the signal bFi+1. The pulse width of thesignal Fi+1 is T−(d+D).

[0182] As described above, after the signal outputted from the NORcircuit 202 b has passed through the two unit delay elements, the pulsewidth of the signal changes from T to T−(d+D). That is, after the signalhas passed through the two unit delay elements, the pulse width of thesignal becomes shorter by the amount of delay in the unit delayelements. In a delay line composed of unit delay elements, when thepulse width become shorter as described above, the pulse might disappearin the worst state.

[0183] Furthermore, when NAND circuits are used in place of the NORcircuits 201 b and 202 b, the pulse width of the signal passed throughthe unit delay elements becomes greater because of the logic of the NANDcircuit. Thus, in the worst state, adjacent pulse signals might connectwith each other.

[0184] The SAD synchronizing circuit using the delay line determines theamount of delay in one cycle between a first clock signal and a secondclock signal and actually delays the second clock, thereby synchronizingthe second clock signal with a third clock signal. That is, thesynchronizing circuit is designed to achieve synchronization after twoperiods. Therefore, the SAD synchronizing circuit has the advantage thatthe synchronizing speed (Lock-in Time) is fast. If the first clocksignal or the second clock signal has jitters (or a phase shift in theclock signal), they have the disadvantage of amplifying the jitters.

[0185] To overcome the problems, a method of suppressing theamplification of jitters by calculating the average in two cyclesbetween the first clock signal and the third clock signal has beenproposed. Specifically, two signals corresponding to an odd-numberedclock signal and an even-numbered clock signal are used as the controlsignal for the state holding circuit. NOR circuits are used as theinverter circuits constituting unit delay elements for forward pulsesignals and backward pulse signals. In this way, the amplification ofjitters is suppressed by averaging the signals in two cycles.

[0186]FIG. 30A shows a unit delay element which uses a NOR circuit 221and to which a forward pulse signal is supplied. FIG. 30B shows a stateholding circuit controlled by odd-numbered signals bRo and So andeven-numbered signals bRe and Se. An odd-numbered state holding circuitis controlled by the signals bRo and So and an even-numbered stateholding circuit is controlled by the signals bRe and Se. The signals bRoand So have twice the period of the signal bpm. The signal bRo hasalmost the same duty ratio as that of the signal bpm, whereas the signalSo has almost half the duty ratio of the signal bpm. FIG. 31 shows aunit delay element which uses the NOR circuit 222 and to which abackward signal is supplied. Although a conventional synchronizingcircuit permits the amount of jitters δ to be amplified to 3δ, thesynchronizing circuit for averaging signals in two cycles suppresses theamplification of jitters to 2δ as shown in FIGS. 30A, 30B, and 31. Sinceeach of the unit delay elements shown in FIGS. 30A, 30B, and 31 iscomposed of a clocked inverter circuit and a NOR circuit, they havedisadvantages in that the pulse width decreases each time the signalpasses through the unit delay element as described earlier. Namely,there is a possibility that a clock signal with a long period or with asmall duty ratio will disappear in the middle of passing through unitdelay elements.

[0187] To overcome this problem, a unit delay element in the sixthembodiment is composed of a circuit for widening the pulse width and acircuit for narrowing the pulse width, which makes the pulse width ofthe input signal of the unit delay element to coincide with that of itsoutput signal.

[0188] Specifically, in the sixth embodiment of FIG. 32, the unit delayelements 14 i and 14 i+1 are composed of clocked inverter circuits 231 aand 232 a for widening the pulse width of the input signal and NORcircuits 231 b and 232 b for narrowing the pulse width.

[0189]FIG. 33 shows the signals at various sections of the unit delayelements 14 i and 14 i+1 of FIG. 32. A case where a signal Fi−1 with thepulse width T is supplied to the input terminal of the clocked invertercircuit 231 a will be considered.

[0190] It is assumed that the amount of delay in the falling of thepulse signal produced by NMOS transistors NM51 and NM52 constituting theclocked inverter circuit 231 a is “d1” and the amount of delay in therising of the pulse signal produced by PMOS transistors PM51 and PM52constituting the clocked inverter circuit 231 a is “d2”. In this case,the falling and rising of the output signal bFi of the clocked invertercircuit 231 a lag behind by “d1” and “d2” from the signal Fi−1,respectively. The pulse width of the signal bFi is T+d2−d1.

[0191] Since the input signal bFi−1 to the NOR circuit 231 b is a signalone stage of unit delay element ahead of the signal bFi, it has thepulse width T and the amount of delay “d1+D”. The amount of delay Doccurs in both the rising and falling of the NOR circuit 231 b. Becausethe logical threshold values are equalized in the NOR circuit 231 b, theamount of delay in the rising is equal to that in the falling.

[0192] The rising of the output signal Fi of the NOR circuit 231 b isdetermined by the signal bFi rising after the signal bFi−1 and lagsbehind by the amount of delay “D” from the rising of the signal bFi. Thefalling of the signal Fi is determined by the signal bFi−1 and lagsbehind by the amount of delay “D” from the rising of the signal bFi−1.Thus, it is equal to the falling of the signal Fi−1. The pulse width ofthe signal Fi is T−(d1+D).

[0193] In the unit delay element 14 i+1, since the signal Fi is suppliedto the input terminal of the clocked inverter circuit 232 a, the fallingof the output signal bFi+1 of the clocked inverter circuit 232 a lagsbehind by the amount of delay “d1” and the rising lags behind by theamount of delay “d2”. The pulse width of the signal bFi+1 is T+d2−2d1−D.The signal bFi+1 and the output signal bFi of the clocked invertercircuit 231 a are supplied to the NOR circuit 232 b. Thus, the rising ofthe output signal Fi+1 of the NOR circuit 232 b is determined by thefalling of the signal bFi+1 falling after the signal bFi and lags behindby the amount of delay “D” from the signal bFi+1. In addition, thefalling of the signal Fi+1 lags behind by the amount of delay “D” fromthe rising of the signal bFi+1 and signal bFi. The pulse width of thesignal Fi+1 is T+d2−2d1−D.

[0194] As described above, after the signal has passed through the twounit delay elements 14 i and 14 i+1, the pulse width of the signalbecomes T+d2−2d1−D. In a case where the amount of delay of each of theclocked inverter circuits 231 a and 231 b is set so that the equationd2=2d1+D may hold, even when the signal has passed through the two unitdelay elements 14 i and 14 i+1, the signal has the pulse width T andtherefore the pulse width remains unchanged. To set the amount of delayto d2=2d1+D, the following method is considered.

[0195] The channel width of each of the NMOS transistors NM51, NM52,NM53 and NM54 of the clocked inverter circuits 231 a and 231 b is madegreater and the channel width of each of the PMOS transistors PM51,PM52, PM53 and PM54 is made narrower. By doing this, the pulse width ofthe signal passed through the clocked inverter circuits 231 a and 231 bgets wider. That is, making the channel width of the NMOS transistorgreater increases the current driving capability of the NMOS transistor,which shortens the rise time of the pulse. In addition, making thechannel width of the PMOS transistor narrower decreases the currentdriving capability of the PMOS transistor, which makes the rise time ofthe pulse longer. As a result, the pulse width of the signal gets wider.

[0196] Now, a method of determining the channel width of the clockedinverter circuits constituting the unit delay element will be explained.

[0197] As shown in FIG. 34A, the unit delay element 14 i is composed ofa clocked inverter circuit 231 a and a NOR circuit 231 b. It isdifficult to achieve optimization by changing the channel width of eachof the transistors constituting the clocked inverter circuit 231 a andNOR circuit 231 b. Therefore, the channel width of each of thetransistors constituting the NOR circuit 231 b is set so as to equalizethe logical threshold values, taking into account the drivingcapabilities of the NMOS transistors and PMOS transistors. After thechannel width of each of the transistors constituting the NOR circuit231 b has been determined, the capacity driven by the NOR circuit 231 bis made almost equal to the capacity driven by the clocked invertercircuit 231 a, taking into account the gate capacity. By doing this, thesum of the channel width (Wp) of the PMOS transistors constituting theclocked inverter circuit 231 a and the channel width (Wn) of the NMOStransistors is determined uniquely. With the sum of the channel widthsWp and Wn fixed (Wp+Wn=constant), the amount of delay “RD” in the risingof the pulse signal and the amount of delay “FD” in the falling of thepulse signal are simulated by changing the channel width Wp or Wn asshown in FIG. 34B. By the simulation, the channel widths Wp and Wn thatequalize the amount of delay “RD” in the rising with the amount of delay“FD” in the falling are determined.

[0198]FIG. 35 shows the result of the simulation. The ordinate axisrepresents the amount of delay “RD” in the rising and the amount ofdelay “FD” in the falling for one stage of unit delay element. Theabscissa axis represents the channel width Wp of the PMOS transistorsconstituting a clocked inverter circuit. With the dimensions that allowthe amount of delay in the rising to cross the amount of delay in thefalling, the pulse width of the signal passed through the unit delayelements is kept constant. When the amount of delay in the rising isgreater than the amount of delay in the falling, the pulse width of thesignal passed through the unit delay elements decreases. Conversely,when the amount of delay in the rising is smaller than the amount ofdelay in the falling, the pulse width of the signal passed through theunit delay elements increases. The present example is based on theassumption that Wp+Wn=9 μm holds, the channel width Wp of a PMOStransistor is 3.5 μm, and the channel width Wn of an NMOS transistor is5.5 μm.

[0199] Conversely, the channel width of the clocked inverter circuit maybe determined and thereafter the sum of the channel width of the PMOStransistor and that of the NMOS transistor in the NOR circuit may bemade constant, thereby determining the channel width of the NOR circuitat which the amount of delay in the rising becomes equal to the amountof delay in the falling.

[0200] Which of the above approaches is better is determined by theabsolute value of the amount of delay. Since the accuracy of thesynchronizing circuit is determined by the amount of delay in the risingper stage of unit delay element, the one with the smaller absolute valueof the amount of delay is better.

[0201] The pulse width of the signal can be made greater by changing notonly the channel width of the transistors but also the channel length ofthe transistors, the threshold voltage, or the voltage of the substratein which the transistors are formed.

[0202] When the channel length of the transistors is changed, thechannel length of the NMOS transistors constituting the clocked invertercircuit is made shorter and the channel length of the PMOS transistorsis made longer.

[0203] When the threshold voltage of the transistors is changed, thethreshold voltages of the NMOS transistors constituting the clockedinverter circuit are made lower and the threshold voltages of the PMOStransistors are made higher.

[0204] When the substrate voltage is changed, the substrate voltage ofthe NMOS transistors constituting the clocked inverter circuit is madehigher and the substrate voltage of the PMOS transistors is made lower.

[0205] The method shown in FIG. 35 is not limited to the determinationof the channel width and may be applied to the determination of thechannel length, threshold voltage, or substrate voltage.

[0206] With the sixth embodiment, a unit delay element is composed of acircuit for widening the pulse width and a circuit for narrowing thepulse width. This enables the pulse width of the input signal of a unitdelay element to coincide with that of its output signal, which preventsthe pulse width of the signal outputted from the unit delay element fromgetting narrower, even when the unit delay element includes a NORcircuit.

[0207] Seventh Embodiment

[0208]FIG. 36 shows a seventh embodiment of the present invention. Inthe seventh embodiment, a unit delay element is composed of a clockedinverter circuit and a NAND circuit. In unit delay elements 14 i, 14 i+1and 14 i+2, clocked inverter circuits 241 a, 242 a and 243 a arecircuits for narrowing the pulse width of signals passing through therespective unit delay elements. In addition, NAND circuits 241 b and 242b are circuits for widening the pulse width of signals passing throughthe respective unit delay elements.

[0209]FIG. 37 shows the signals at various sections in FIG. 36. First,consider a case where a signal Fi−1 with the pulse width T is inputtedto the input terminal of a clocked inverter circuit 241 a. It is assumedthat the amount of delay in the falling of the pulse signal produced bythe NMOS transistors constituting clocked inverter circuits 241 a, 242 aand 243 a is “d1” and the amount of delay in the rising of the pulsesignal produced by the PMOS transistors is “d2”. Then, the amount ofdelay in the falling of and that in the rising of the output signal bFiof the clocked inverter circuit 241 a are “d1” and “d2,” respectively.Thus, the pulse width of the signal bFi becomes T+d2−d1.

[0210] Since the input signal bFi−1 to the NAND circuit 241 b is asignal one stage of unit delay element ahead of the signal bFi, it hasthe pulse width T and the amount of delay “d1+D”. The amount of delay Doccurs in both the rising and falling of the NAND circuits 241 b and 242b. Because the logical threshold values are equalized in the NANDcircuits 241 b and 242 b, the amount of delay in the rising is equal tothat in the falling.

[0211] The rising of the output signal Fi of the NAND circuit 241 b isdetermined by the signal bFi−1 falling before the signal bFi and lagsbehind by the amount of delay “D” from the falling of the signal bFi−1.The falling of the signal Fi is determined by the signal bFi fallingafter the signal bFi−1 and lags behind by the amount of delay “D” fromthe rising of the signal bFi. The pulse width of the signal Fi isT+(d1+D).

[0212] In the next unit delay element 14 i+1, the signal Fi is suppliedto the input terminal of the clocked inverter circuit 242 a. As aresult, the falling of the output signal bFi+1 of the clocked invertercircuit 242 a lags behind by the amount of delay “d1” from the signal Fiand the rising lags behind by the amount of delay “d2” from the signalFi. The pulse width of the signal bFi+1 is T+d2+D. The signal bFi+1 andthe signal bFi are supplied to the AND circuit 242 b. The rising of theoutput signal Fi+1 of the NAND circuit 242 b is determined by thefalling of the signal bFi+1 falling before the signal bFi and lagsbehind by the amount of delay “D” from the signal bFi+1. In addition,the falling of the signal Fi+1 lags behind by the amount of delay “D”from the rising of the signal bFi+1 rising after the signal bFi. Thepulse width of the signal Fi+1 is T+d2+D.

[0213] In the next unit delay element 14 i+2, the signal Fi+1 issupplied to the input terminal of the clocked inverter circuit 243 a. Asa result, the falling of the output signal bFi+2 of the clocked invertercircuit 243 a lags behind by the amount of delay “d1” from the signalFi+1 and the rising lags behind by the amount of delay “d2” from thesignal Fi+1. The pulse width of the signal bFi+1 is T−d1+2d2+D.

[0214] As described above, after the signal has passed through the twounit delay elements 14 i and 14 i+1, and the clocked inverter circuit243 a, the pulse width of the signal becomes T−d1−2d2+D. In a case wherethe amount of delay is set so that the equation d1=2d2+D may hold, evenwhen the signal has passed through the two unit delay elements 14 i and14 i+1 and the inverter circuit 243 a, the signal has the pulse width Tand therefore the pulse width remains unchanged. To set the amount ofdelay to d1=2d2+D, the following method is considered.

[0215] The channel width of each of the NMOS transistors NM61, NM62,NM63, NM64, NM65 and NM66 of the clocked inverter circuits 241 a, 242 aand 243 a is made narrower and the channel width of each of the PMOStransistors PM61, PM62, PM63, PM64, PM65 and PM66 is made wider. Withthis setting, the pulse width of the signal passed through the clockedinverter circuits 241 a, 242 a and 243 a gets narrower. That is, makingthe channel width of the NMOS transistor narrower decreases the currentdriving capability of the NMOS transistor, which makes the rise time ofthe pulse longer. In addition, making the channel width of the PMOStransistor wider increases the current driving capability of the PMOStransistor, which makes the rise time of the pulse shorter. As a result,the effective pulse width of the signal gets narrower.

[0216] The means for narrowing the pulse width produces the same effectsby changing not only the channel width but also at least one of thechannel length, the threshold voltage, and the voltage of the substrate.

[0217] When the channel length is changed, the channel length of theNMOS transistors constituting the clocked inverter circuits 241 a, 242 aand 243 a is made longer and the channel length of the PMOS transistorsis made shorter.

[0218] When the threshold voltage of the transistors is changed, thethreshold voltages of the NMOS transistors constituting the clockedinverter circuits 241 a, 242 a and 243 a are made higher and thethreshold voltages of the PMOS transistors are made lower.

[0219] When the substrate voltage is changed, the substrate voltage ofthe NMOS transistors constituting the clocked inverter circuits 241 a,242 a and 243 a is made lower and the voltage of the substrate in whichthe PMOS transistors are formed is made higher.

[0220] With the seventh embodiment, a unit delay element is composed ofclocked inverter circuits and a NAND circuit. The clocked invertercircuits decrease the pulse width of the signal by the length by whichthe pulse width of the signal is increased by the NAND circuit. Thisprevents the pulse width of the signal passed through the unit delayelement from getting wider.

[0221] The methods in the sixth and seventh embodiments need notincorporate a new circuit into a unit delay element and therefore hasthe advantage of preventing the area occupied by the circuit fromincreasing.

[0222] In the sixth and seventh embodiments, the first delay line forforward pulse signals that constitutes the synchronizing circuit hasbeen explained. By constructing the second delay line for backward pulsesignals similarly, the pulse width of a backward pulse signal can alsobe kept constant before and after the unit delay element.

[0223] Furthermore, a synchronizing circuit may be formed byconstructing a first delay line for transferring forward pulse signalsand a second delay line for transferring backward pulse signals usingthe unit delay elements explained in the sixth and seventh embodiments.

[0224] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A delay circuit comprising: a clocked invertercircuit to which a first pulse signal is supplied; and a logic circuitto which a second pulse signal outputted from said clocked invertercircuit and an inverted signal of said first pulse signal are supplied,wherein said clocked inverter circuit changes a pulse width of saidfirst pulse signal in a direction opposite to a direction in which apulse width of a third pulse signal outputted from said logic circuitchanges.
 2. The delay circuit according to claim 1, wherein said logiccircuit is a NOR circuit and said clocked inverter circuit delays atrailing edge of said third pulse signal.
 3. The delay circuit accordingto claim 1, wherein said logic circuit is a NAND circuit and saidclocked inverter circuit delays a leading edge of said third pulsesignal.
 4. The delay circuit according to claim 1, wherein said clockedinverter circuit is composed of an NMOS transistor and a PMOS transistorand at least one of a channel width, channel length, threshold voltage,and substrate voltage of the NMOS is different from a channel width,channel length, threshold voltage, and substrate voltage of the PMOStransistors.
 5. The delay circuit according to claim 4, wherein a ratioof a current driving capability of said PMOS transistor to a currentdriving capability of said NMOS transistor is set to a value other thanone and a rise time of a pulse signal is made different from a decaytime of the pulse signal.
 6. A delay circuit comprising: an invertercircuit controlled by a clock signal to which a first pulse signal issupplied; and a logic circuit to which a second pulse signal outputtedfrom said inverter circuit and an inverted signal of said first pulsesignal are supplied, wherein said inverter circuit changes a pulse widthof said first pulse signal in a direction opposite to a direction inwhich a pulse width of a third pulse signal outputted from said logiccircuit changes.